1. Field of the Invention
This invention relates to a data processing apparatus for controlling access to a memory by a central processing unit (CPU).
2. Description of the Related Art
One method for transferring data within a computer system utilizes Direct Memory Access (DMA) transfer for directly sending data between each device (for example, Input/Output (I/O) devices) and a memory (for example, a Random Access Memory (RAM)) without transiting through the CPU. The term, DMA transfer as used here, refers to the operation from reading of data from each device, to the writing of that data into a memory within the system. Moreover, the operation of writing data into a memory within the system by DMA transfer is hereafter referred to as DMA write. A DMA controller (hereafter called DMAC) controls the DMA transfer. A bus arbiter mediates the buses utilized in DMA transfer. The CPU can therefore access regions other than memory regions being used for DMA transfer and can execute other processing during DMA transfer. The CPU for example can access regions other than the DMA transfer destination address and execute other processing while data sent from an I/O device via DMA transfer is being written into a memory. When reading data sent via DMA transfer, the CPU can access the DMA transfer destination address after checking that DMA transfer has been completed, and read the data (hereafter called, CPU Read) that was written into the memory via DMA transfer. In this case, the CPU of the prior art can check that DMA transfer is complete, by a DMAC making an interrupt to the CPU.
However, execution of the interrupt processing routine has become faster in recent years due to improved CPU processing speeds. The data transfer speed of data transfer units however, has not drastically improved to keep pace with the multiple functions of integrated circuits. The CPU might therefore sometimes access the DMA write destination address in the applicable memory and read data, before data can be written by DMA write. In that case, the CPU reads the (old) data from the memory before the (new) data has been written by DMA write.
One technology for resolving this type of problem is disclosed in JP-A 6(1994)-231023. In the method described in JP-A No. 231023/1995, an access control device temporarily stores the address of the DMA transfer destination in a buffer, compares that address with an address sent during CPU access, and control the reading by the CPU based on these comparison results.
FIG. 8 is a block diagram showing the internal structure of the access control device 202 and the system structure of a system using the access control device 202 as disclosed in JP-A No. 231023/1995. The access control device 202 is installed between the processor 201 and the I/O device 205 as shown in FIG. 8. A buffer 212 stores the address data of the transfer destination during DMA transfer (write) onto the main memory device 203 from the I/O device 205. A buffer 211 stores the address data of the read destination when the processor 201 is accessing (reading) the main memory device 203.
The access control device 202 includes a comparator 213 for comparing the address within the buffer 212 with the address within the buffer 211 and, an access control unit 214 for controlling the CPU read process according to the results from the comparator 213. The comparator 213 here compares all entries in the buffer 212, with entries from the earliest string in the buffer 211 (next entries to be output). If both addresses are same, then the access control unit 214 stops the CPU access to prevent it from overtaking the DMA transfer.
Technology for acquiring information from an internal bus on the other hand, is disclosed in JP-A 2001-134467.
The present inventor has recognized that in the technology disclosed in JP-A 6(1994)-231023, the CPU accessing of the memory device might overtake the DMA (transfer) when the DMA transfer is performed via buses in a hierarchical structure using bus bridges. In the structure shown in FIG. 8 where another bus is connected by a bus bridge to the bus 204, the case is described where an I/O device connected to another bus is performing DMA transfer to the main memory device 203 via the bus bridge. Usually a buffer (first-in/first-out (FIFO) buffer) is installed on bus bridges connecting between buses to allow smooth data transfer between buses operating at different transfer speeds. In this case, arrival at the buffer 212 of address data sent for DMA transfer from I/O devices is delayed due to being held in the buffer within the bus bridge.
The read address data from the processor 201 might be input to the buffer 211 earlier than the address data for DMA write onto the main memory device 203 arrives at the buffer 212, so that the access control unit 214 cannot stop access from the processor 201. The present inventor therefore took note of the fact that the technology disclosed in JP-A No. 231023/1995 has the problem that the possibility of access from the CPU overtaking the DMA transfer data writing still remains during DMA transfer executed via a structure including buffers (delay elements) such as bus bridges. The buffer within the bus bridge also utilizes the FIFO method and the size of that buffer is usually set based on the timing and difference in the input/output speed of the data being handled. The present inventor also noticed that the possibility of reading by the CPU occurring faster (overtaking) than DMA write, increases when the buffer is large.